In recent years, the RISC-V architecture has gained significant traction amongst a wide variety of chipmakers. It may be less than a decade since the first RISC-V workshops were held, but today the open architecture is finding its way into a myriad of chips and technologies industry-wide. It was just a couple of weeks ago when tech giants Google and Qualcomm announced they’d be teaming up on a RISC-V based Snapdragon Wearable Platform for future Wear OS devices, and today – with the RISC-V Summit currently underway in Santa Clara – silicon design, verification and IP leader Synopsys has announced an array of new 32-bit and 64-bit ARC-V Processor IP targeting embedded automotive, storage, and IoT applications. The IP includes the Synopsys ARC-V RMX (Ultra Low Power Embedded, 32-bit processor), the ARC-V RHX (Real-Time, 32-bit), and the Synopsys ARC-V RPX (64-bit multi-core host processor).
Synopsys is well known for its leadership role in the EDA (Electronic Design Automation) space, where its AI-infused toolset is leveraged across the industry by silicon kingpins like Intel, NVIDIA and AMD, and fledgling startups alike. And RISC-V is an open standard Instruction Set Architecture (ISA) maintained by RISC-V International. RISC-V is often viewed as an alternative to other licensable architectures, like Arm for example, but due its open-source licensing model, customization flexibility, and (typically) lower cost, RISC-V offers a number of key advantages.
Synopsys Adopts RISC-V And Expands Its ARC Processor IP Portfolio
“The global adoption of the open-standard RISC-V ISA is defining the future of semiconductor design, and it’s through the commitment and advancements from technology innovators like Synopsys that RISC-V continues to accelerate the future of computing,” said Calista Redmond, CEO, RISC-V International. “Synopsys ARC-V Processor IP, combined with the company’s cooptimized EDA and verification solutions, contribute to greater flexibility and choice in the RISC-V ecosystem for the benefit of chip design across industries.”
Synopsys has a long history of expertise in processor IP development and has offered various iterations of its ARC processor IP for many years. This new RISC-V family, however, moves to a totally new instruction set and consists of custom high-performance, mid-range, and ultra-low power options, including specialized functional safety versions (optimized for ISO 26262 ASIL-B & D Safety Implementations). The new RISC-V based ARC-V Processor IP is also extensible, which is to say customers can develop custom instructions for the ISA if the need arises, and Synopsys claims the IP offers leading performance-per-watt efficiency as well.
EDA Design, Test, Verification And Software Ecosystem At The Ready For RISC-V
Another key value add for the ARC-V Processor IP is that the company’s Synopsys.ai full-stack AI-driven EDA software and tool suite and Fusion QuickStart Implementation Kits are optimized for the designs to provide an immediate development and verification environment to accelerate time to market and ultimately fully optimized ARC-V-based chips and SoCs. In addition, the Synopsys MetaWare software development toolchain is ready to help programmers develop optimized code for ARC-V Processor IP.
Synopsys 32-bit ARC-V RMX embedded processor IP should be made available in Q2 of next year, with the 32-bit Synopsys ARC-V RHX real-time processor and 64-bit ARC-V RPX host processor IP due to arrive a little later in the second half of 2024. Representatives from Synopsys have informed me, however, that customers have already shown interest, with one major automotive customer already on-board. Over and above its new IP announcements, Synopsys also disclosed that it has joined the RISC-V International Board of Directors and Technical Steering Committee to further advance the RISC-V instruction set and work toward boosting adoption moving forward.