Although chiplets have recently broken into the semiconductor limelight in a big way, Intel’s Programmable Solutions Group (PSG) has relied on chiplet technology for its Field Programmable Gate Arrays (FPGAs) since 2016, starting with the announcement of the company’s first Intel Stratix 10 devices. These FPGAs use Intel’s embedded multi-die interconnect bridge (EMIB) packaging technology to connect the main FPGA die to a variety of interface and memory chiplets. Intel continued using this same EMIB packaging technology to incorporate chiplets into its next-generation Intel Agilex FPGAs as well. One significant advantage of the chiplet-based design approach that’s especially important for Intel PSG is that the technology allows Intel to rapidly add new members to its FPGA product families. This rapid development of new family members is of great benefit to Intel’s FPGA customers, for a variety of reasons.
Chiplets have allowed Intel PSG to add many new features to its FPGAs including:
- February 2018: 58Gbps PAM4 transceivers
- August 2019: PCIe 4.0 support
- November 2019: Industry’s first FPGA with more than 10 million logic elements
- April 2022: PCIe 5.0 x16 operation at 32 billion transfers/second
- September 2022: Direct analog/digital radio-frequency (RF) conversion at 64 billion conversions/second
- March 2023: 116Gbps PAM4 transceivers
- May 2023: PCIe 5.0 and CXL hardware support
According to Deepali Trehan, VP and General Manager of Intel PSG, the capabilities enabled by chiplets in Intel’s FPGAs is a major reason why customers decide to use these FPGAs in their system designs. Use of chiplets in its FPGAs allows Intel to provide technologically advanced features, such as those listed above, before they’re available in other devices, with reduced development risk, and with greatly reduced development time.
One such long-term customer is BittWare, which develops FPGA-based acceleration cards based on the Peripheral Component Interconnect Express (PCIe) bus standard. BittWare has been developing these PCIe acceleration cards based on Intel FPGAs for at least 20 years. These PCIe cards are used for computational acceleration, networking, and sensor fusion, and are paired frequently with Intel Xeon CPUs in edge applications where they’re used as high-performance data processors and input/output (I/O) engines.
Craig Petrie, VP and GM of Molex’s BittWare business unit, notes that the use of chiplets in FPGAs has brought new I/O capabilities to FPGAs faster than would otherwise be possible. This fast time to market at the component level allows BittWare to achieve similarly fast time to market with its board-level products. Petrie specifically notes that chiplets have allowed BittWare to deliver accelerator cards with PCIe 4.0, PCIe 5.0, Compute Express Link (CXL), and high-speed Ethernet ports in rapid succession.
“Tiles (chiplets) take away a big problem,” says Petrie, explaining that if a new monolithic FPGA must be designed for each new I/O standard, such as the various generations of PCIe and Ethernet standards, there are inevitably some minor variations in the FPGA’s overall design compared to the previous generation. These minor variations require design revisions on BittWare’s part, and these revisions will require additional design time. By using chiplets for these I/O functions, the central portion of the FPGA, the main silicon die, can remain unchanged. Consequently, chiplets allow a semiconductor vendor such as Intel to accommodate these new I/O features more quickly and eliminate the need to redesign the main FPGA die. “This de-risks our designs,” explained BittWare’s Petrie.
Seth Friedman – co-founder, president, and CEO of Liquid-Markets-Solutions (LMS), has a similar opinion regarding chiplet-based FPGAs. His company has developed a network interface card (NIC) called the “ÜberNIC,” which was initially developed for the financial market’s high-speed-trading segment. In this market, every microsecond counts, because slower trades simply don’t make as much profit as faster ones. Consequently, LMS developed a fast, hardware-based, full Ethernet protocol stack and embodied it in an Intel FPGA on its network card to meet the low-latency requirements of the financial community.
However, LMS quickly discovered that many other companies involved with telecommunications, computing, broadcasting, research, and academia also needed similarly speedy NICs for applications ranging from test equipment to automated vision systems. Cloud services providers, hyperscalers, also need high-speed NICs for their data centers.
Friedman notes that chiplets in FPGAs have given his company a time-to-market advantage through PCIe 5.0 interface ports and will be doing the same for CXL 1.1 and 2.0. “All due to chiplet technology,” explained Friedman. He also pointed out another chiplet advantage that’s important to LMS: transceiver density. Using chiplet-based FPGAs with many high-speed Ethernet transceivers allows LMS to plug two to four times as many optical fiber pairs into one of its ÜberNICs.
LMS employs Intel FPGAs for more than their I/O benefits, however. The programmable hardware in the FPGA allows the company to construct high-speed Ethernet protocol engines, as explained above, but there’s room left over in the FPGA to incorporate additional functions of great value to the end customer. For example, LMS has implemented Intel’s Precision Time Measurement (PTM) capability, found in Intel 4th Generation Xeon Scalable CPUs, into its ÜberNIC card. PTM enables precise coordination of events across multiple components with independent local time clocks. This precision time capability is of great benefit for time-stamping high-speed financial transactions, but it’s also beneficial wherever data streams must have a precise time stamp. “No traditional NIC can offer this,” says Friedman. The task requires the programmable hardware available in FPGAs.
Customers such as Bittware and LMS are one factor that keeps chiplets on Intel’s FPGA roadmap. Currently, Intel PSG’s FPGAs have relied on EMIB packaging technology and an Intel-developed bus protocol called the Advanced Interface Bus (AIB), which Intel subsequently contributed to the CHIPS Alliance as an open-source, royalty-free standard. However, the Intel PSG roadmap extends beyond the present-day use of EMIB and AIB.
“UCIe is important for our next-generation FPGAs,” says Intel’s Trehan, referring to the Universal Chiplet Interconnect Express (UCIe) standard now being developed by UCI Express, an industry consortium and nonprofit corporation established last March by Intel, along with Advanced Semiconductor Engineering Inc. (ASE), AMD, Arm, Google Cloud, Meta, Microsoft Corp., Qualcomm Inc., Samsung, and Taiwan Semiconductor Manufacturing Company (TSMC). With UCIe as a chiplet interconnect standard, Trehan envisions a marketplace of chiplets, manufactured by multiple foundries using different semiconductor process nodes, which Intel can then use to enable the assembly of FPGAs and other IC types with more exotic electronics capabilities including high-power gallium nitride (GaN) drivers and high-speed, optical I/O incorporated directly into the FPGA package. These new capabilities would result in entirely new application horizons for FPGAs.
The use of chiplets in high-end semiconductor devices is now well established, backed by years of practical experience as pioneered by FPGAs. Chiplets are now appearing in CPUs and GPUs as well. TIRIAS Research believes that the use of chiplets will continue and grow in these high-end devices to add new features and new capabilities, boost performance, and extend the life of Moore’s Law while addressing customers’ time-to-market needs. The advent of a die-to-die interface standard for chiplets developed by an industry-wide consortium – UCIe – will only accelerate this trend. There’s no going back. Meanwhile, monolithic construction remains the least expensive packaging alternative and will continue to dominate in the manufacture of lower cost semiconductor devices.
For more information on chiplets, see:
The Chiplet’s Time Is Coming, It’s Here, Or Not.
Are Chiplets Enough to Save Moore’s Law?
Intel Takes Control of Communications Hill with Analog-Enabled FPGA Portfolio
Intel’s Chiplet Leadership Delivers Industry-Leading Capabilities at an Accelerated Pace